Introduction to Substrate Noise in Soi Cmos Integrated Circuits

In this paper an introduction to substrate noise in silicon on insulator (SOI) is given. Differences between substrate noise coupling in conventional bulk CMOS and SOI CMOS are discussed and analyzed by simulations. The efficiency of common substrate noise reduction methods are also analyzed. Simulation results show that the advantage of the substrate isolation in SOI is only valid up to a frequency that highly depends on the chip structure. In bulk, guard bands are normally directly connected to the substrate. In SOI, the guard bands are coupled to the substrate via the parasitic capacitance of the silicon oxide. Therefore, the efficiency of a guard may be much larger in a conventional bulk than in SOI. One opportunity in SOI is that a much higher resistivity of the substrate can be used, which results in a significantly higher impedance up to a frequency where the coupling is dominated by the capacitive coupling of the substrate.